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Full list of papers

Journals

J. Nunez-Yanez, "Fused Architecture for Dense and Sparse Matrix Processing in TensorFlow Lite," in IEEE Micro, 2022, doi: 10.1109/MM.2022.3196705.

Andrés Rodríguez, Angeles G. Navarro, Kris Nikov, José L. Núñez-Yáñez, Ruben Gran, Darío Suárez Gracia, Rafael Asenjo: Lightweight asynchronous scheduling in heterogeneous reconfigurable systems. J. Syst. Archit. 124: 102398 (2022)

Jose Nunez-Yanez, Mohammad Hosseinabady,Sparse and dense matrix multiplication hardware for heterogeneous multi-precision neural networks,Array,Volume 12,2021,

Shen, Z.; Howard, N.; Nunez-Yanez, J. Big–Little Adaptive Neural Networks on Low-Power Near-Subthreshold Processors. J. Low Power Electron. Appl. 2022, 12, 28. https://doi.org/10.3390/jlpea12020028

Jose Nunez-Yanez, Neil Howard,”Energy-efficient neural networks with near-threshold processors and hardware accelerators”, Journal of Systems Architecture,2021,102062, https://doi.org/10.1016/j.sysarc.2021.102062.

Kwan, E.Y.L.; Nunez-Yanez, J. Entropy-Driven Adaptive Filtering for High-Accuracy and Resource-Efficient FPGA-Based Neural Network Systems. Electronics 2020, 9, 1765. https://doi.org/10.3390/electronics9111765

J. Nunez-Yanez, "Energy Proportional Neural Network Inference with Adaptive Voltage and Frequency Scaling," in IEEE Transactions on Computers, vol. 68, no. 5, pp. 676-687, 1 May 2019.doi: 10.1109/TC.2018.2879333, 100% own contribution

Yang Zhang, Paul Hutchinson, Nicholas A.J. Lieven, Jose Nunez-Yanez, Adaptive event-triggered anomaly detection in compressed vibration data, Mechanical Systems and Signal Processing, Volume 122,2019,Pages 480-501,ISSN 0888-3270 15% contribution with industry collaboration

M. Hosseinabady and J. L. Nunez-Yanez, "A Streaming Dataflow Engine for Sparse Matrix-Vector Multiplication using High-Level Synthesis," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. doi: 10.1109/TCAD.2019.2912923 25% contribution

Rodríguez, A, Navarro, A, Asenjo, R, Corbera, F, Gran, R, Suárez, D & Nunez-Yanez, J, 2019, ‘Exploring heterogeneous scheduling for edge computing with CPU and FPGA MPSoCs’. Journal of Systems Architecture, vol 98., pp. 27-40, 10% contribution with international collaborators

Rodríguez, A, Navarro, A, Asenjo, R, Corbera, F, Gran, R, Suarez, D & Nunez-Yanez, J, 2019, ‘Parallel Multiprocessing and Scheduling on the Heterogeneous Xeon+FPGA Platform’. Journal of Supercomputing. 15% contribution with international collaborators

Qianqiao Chen, Vaibhawa Mishra, Jose Nunez-Yanez, and Georgios Zervas, “Reconfigurable Network Stream Processing on Virtualized FPGA Resources,” International Journal of Reconfigurable Computing, vol. 2018, Article ID 8785903, 11 pages, 2018. https://doi.org/10.1155/2018/8785903. 10% own contribution with industry collaboration.

Mohammad Hosseinabady and Jose Luis Nunez-Yanez. 2018. Dynamic Energy Management of FPGA Accelerators in Embedded Systems. ACM Trans. Embed. Comput. Syst. 17, 3, Article 63 (May 2018), 26 pages. DOI: https://doi.org/10.1145/3182172. 30% own contribution

Nunez-Yanez, J, Amiri, S, Hosseinabady, M, Rodríguez, A, Asenjo, R, Navarro, A, Suarez, D & Gran, R, Supercomput (2019) 75: 4078. 50% own contribution. https://doi.org/10.1007/s11227-018-2367-9 80% own contribution with international collaborators

Bin Zainol, MA & Nunez-Yanez, J, 2018, ‘“Extending the PCIe Interface with Parallel Compression/Decompression Hardware for Energy and Performance Optimization”’. International Journal on Computer Science & Communication Engineering (IJFRSCE), vol 4., pp. 405-419. 30% own contribution

Jose Nunez-Yanez, Adaptive voltage scaling in a heterogeneous FPGA device with memory and logic in-situ detectors, Microprocessors and Microsystems, Volume 51, 2017, Pages 227-238, ISSN 0141-9331, http://dx.doi.org/10.1016/j.micpro.2017.04.021. 100% own contribution

Qianqiao Chen, Vaibhawa Mishra, Jose Nunez-Yanez, and Georgios Zervas, “Reconfigurable Network Stream Processing on Virtualized FPGA Resources,” International Journal of Reconfigurable Computing, vol. 2018, 11 pages, 2018. doi:10.1155/2018/8785903 10% own contribution with industry collaborators

Felipe Galindo Sanchez, Jose Nunez-Yanez, Energy proportional streaming spiking neural network in a reconfigurable system, Microprocessors and Microsystems, Volume 53, 2017, Pages 57-67, ISSN 0141-9331, http://dx.doi.org/10.1016/j.micpro.2017.06.018. 40% own contribution with international collaborator.

Nunez-Yanez, J. , M. Hosseinabady and A. Beldachi, "Energy Optimization in Commercial FPGAs with Voltage, Frequency and Logic Scaling," in IEEE Transactions on Computers, vol. 65, no. 5, pp. 1484-1493, May 1 2016.,doi: 10.1109/TC.2015.2435771 80% own contribution

Eugenio, JCM, McGeehan, JP & Nunez-Yanez, JL, 2015, ‘Biologically compatible neural networks with reconfigurable hardware’. Microprocessors and Microsystems, vol 39., pp. 693-703 30% own contribution

Nunez-Yanez, J., "Adaptive Voltage Scaling with in-situ Detectors in Commercial FPGAs," Computers, IEEE Transactions on , vol.PP, no.99, pp.1,1, 0, doi: 10.1109/TC.2013.73, Jan 2015. 100% own contribution

18. Nunez-Yanez, J. L. & Lore, ‘Enabling accurate modeling of power and energy consumption in an ARM-based System-on-chip’ Elsevier Microprocessors and Microsystems. Vol. 37, No. 3, p. 319-332, Jan 2014. 80% own contribution with ARM industry collaboration

Beldachi, Arash Farhadi; Nunez-Yanez, Jose L.: 'Run-time power and performance scaling in 28 nm FPGAs', IET Computers & Digital Techniques, 2014, DOI: 10.1049/iet-cdt.2013.0117, IET Digital Library, http://digital-library.theiet.org/content/journals/10.1049/iet-cdt.2013.0117. 40% own contributions

Beldachi, Arash Farhadi; Hollis, Simon; Nunez-Yanez, Jose L.: 'eXtended Torus routing algorithm for networks-on-chip: a routing algorithm for dynamically reconfigurable networks-on-chip', IET Computers & Digital Techniques, 2014, 8, (3), p. 148-162, DOI: 10.1049/iet-cdt.2013.0087, 30% own contribution, IET Digital Library, http://digital-library.theiet.org/content/journals/10.1049/iet-cdt.2013.0087,

Chen, J.; Nunez-Yanez, J.L.; Achim, A., "Bayesian Video Super-Resolution With Heavy-Tailed Prior Models," Circuits and Systems for Video Technology, IEEE Transactions on , vol.24, no.6, pp.905,914, June 2014, 20% own contribution, doi: 10.1109/TCSVT.2014.2302549

Beldachi A.F.; Hosseinabady, M.; Nunez-Yanez, J., “Configurable Router Design for Dynamically Reconfigurable Systems based on the SoCWire NoC,” International Journal of Reconfigurable and Embedded Systems (IJRES), vol. 2, no. 1, March 2013. 30% own contribution

Xiaolin Chen, Nishan Canagarajah, Jose L. Nunez-Yanez, Raffaele Vitulli, Lossless video compression based on backward adaptive pixel-based fast motion estimation, Signal Processing: Image Communication, Available online 7 July 2012, ISSN 0923-5965, 10.1016/j.image.2012.06.004. 30% own contribution with industry collaboration ESA

Atukem Nabina, Jose Luis Nunez-Yanez, “Adaptive Voltage Scaling in a Dynamically Reconfigurable FPGA-Based Platform”, ACM Trans. Reconfigurable Technol. Syst. 5, 4, Article 20 (December 2012), 22 pages. DOI=10.1145/2392616.2392618. 60% own contribution

Hosseinabady, M.; Nunez-Yanez, J.L., "Fast and low overhead architectural transaction level modelling for large-scale network-on-chip simulation," Computers & Digital Techniques, IET , vol.6, no.6, pp.384,395, November 2012. doi: 10.1049/iet-cdt.2012.0001 20% own contribution

Jin Chen; Nunez-Yanez, J.; Achim, A., "Video Super-Resolution Using Generalized Gaussian Markov Random Fields," Signal Processing Letters, IEEE , vol.19, no.2, pp.63,66, Feb. 2012, doi: 10.1109/LSP.2011.2178595, 20% own contribution

Spiteri, T.; Núńez-Yáńez, J., "Scalable video coding with multi-layer motion vector palettes," Image Processing, IET , vol.6, no.9, pp.1319,1330, December 2012, doi: 10.1049/iet-ipr.2012.0048 40% own contribution

Nunez-Yanez, J.L.; Nabina, A.; Hung, E.; Vafiadis, G.; , "Cogeneration of Fast Motion Estimation Processors and Algorithms for Advanced Video Coding," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , vol.20, no.3, pp.437-448, March 2012, 80% own contribution

Hosseinabady, M.; Nunez-Yanez, J.L.; , "Run-time stochastic task mapping on a large scale network-on-chip with dynamically reconfigurable tiles," Computers & Digital Techniques, IET , vol.6, no.1, pp.1-11, January 2012, 50% own contribution

Chen, J., Nunez-Yanez, J., Achim, A.: "Video Super-resolution Using Generalized Gaussian Markov Random Fields," IEEE Signal Processing Letters, Vol. 19, Feb. 2012. 15% own contribution

Jose L. Nunez-Yanez, Spiteri, T.; Vafiadis, G.; , "Multi-standard reconfigurable motion estimation processor for hybrid video codecs," Computers & Digital Techniques, IET , vol.5, no.2, pp.73-85, March 2011. 80% own contribution

Zhang, Y.; Nunez-Yanez, J.; Mcgeehan, J.; Kelly, S.; Regan, E.; , "Biophysically Accurate Foating Point Neuroprocessors for Reconfigurable Logic," Computers, IEEE Transactions on , vol.PP, no.99,pp.1, doi: 10.1109/TC.2011.257, 30% own contribution

Edward M Regan, James B Uney, Andrew D Dick, Yiwei Zhang, Jose Nunez-Yanez, Joseph P McGeehan, Frederik Claeyssens, Stephen Kelly, “Differential patterning of neuron, glial and neural progenitor cells on phosphorus-doped and UV irradiated diamond-like carbon”, Elsevier Biomaterials, 31 (2). pp. 207-215. 2010. ISSN 0142-9612. 10% own contribution

Xiaolin Chen, Nishan Canagarajah, Jose Nunez-Yanez, 'Backward Adaptive Pixel-Based Fast Predictive Motion Estimation', IEEE Signal Processing Letters(16), No. 5, , pp. 370-373. May 2009. 20% own contribution

Xiaofeng Wu; Chouliaras, V.A.; Nunez-Yanez, J.L.; Goodall, R.M., 'A Novel DeltaSigma Control System Processor and Its VLSI Implementation', Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , vol.16, no.3, pp.217-228, March 2008. 20% own contribution

V.A.Chouliaras,V.M.Dwyer, S.Agha, J.L.Nunez-Yanez, D. Reisis, 'Customization of an embedded RISC CPU with SIMD extensions for video encoding: A case study', Integration, the VLSI Journal archive, Vol. 41 , Issue 1, no. 17, pp. 135-152, January 2008. 20% own contribution with international collaboration (Athens university)

Nunez-Yanez, J.L.; Edwards, D.; Coppola, A.M., "Adaptive routing strategies for fault-tolerant on-chip networks in dynamically reconfigurable systems," Computers & Digital Techniques, IET , vol.2, no.3, pp.184-198, May 2008. 95% own contribution with industry collaboration (ST Micro)

V.A.Chouliaras, J.L Nunez-Yanez ‘Thread Parallel MPEG-2 and MPEG-4 encoders for shared-memory SoC Multiprocessors’ , International Journal of Computers and Applications, 2007 Issue 4, DOI:10.2316/Journal.202.2007.4.202-2017. 20% own contribution

Xiaofeng Wu, Vassilios Chouliaras, J.L. Nunez-Yanez, Roger Goodall, Tanya Vladimirova, “A Novel Processor Architecture for Real-Time Control”, Lecture Notes in Computer Science, Vol. 4186, pp. 270-280, 2006. 10% own contribution

J.L Nunez-Yanez, V.A.Chouliaras, ‘Gigabyte per Second Streaming Lossless Data Compression Hardware Based on a Configurable Variable-Geometry CAM Dictionary’, IEE Proceedings - Computers and Digital Techniques, Vol. 153, Issue: 1, pp. 47-58, January 2006. 95% own contribution

J.L Nunez-Yanez, V.A.Chouliaras, D.Alfonso, F.Rovati, ‘Hardware Assisted Rate Distortion Optimization with Embedded CABAC Accelerator for the H.264 Advanced Video Codec’, IEEE Transactions on Consumer Electronics, Vol. 52, no. 2, pp. 590-598, May 2006. 95% own contribution with industry collaboration (ST Micro)

J.L Nunez-Yanez, V.A.Chouliaras, ‘A Configurable Statistical Lossless Compression Core Based on Variable Order Modelling and Arithmetic Coding’, IEEE Transactions on Computers, vol. 54, no. 11, pp. 1345-1359, Nov., 2005. 95% own contribution

V.A.Chouliaras, J.L Nunez-Yanez, F. Rovati, D. Alfonso, ‘A Multi-standard Video Coding Accelerator Based on a Vector Architecture’, IEEE Transactions on Consumer Electronics, Vol 51, No. 1, pp. 160-167, February 2005. 30% own contribution with industry collaboration (ST Micro)

J.L Nunez-Yanez, V.A.Chouliaras, ‘High-Performance Arithmetic Coding VLSI Macro for the H264 Video Compression Standard’, IEEE Transactions on Consumer Electronics, Vol 51, No. 1, pp. 144-151, February 2005. 95% own contribution

Chouliaras, V.A.; J.L Nunez-Yanez., Koutsomyti, K. Parr, S.R. Mulvaney, D.J. Datta, S, 'Development of custom vector accelerator for high-performance speech coding', IEE Electronic Letters, Page(s): 1559- 1560, Vol. 40, Issue: 24, Nov. 2004. 30% own contribution

M. Milward, J.L. Nunez-Yanez, D. Mulvaney, ‘Design and Implementation of a Lossless Parallel High-Speed Data Compression System’, IEEE Transactions on Parallel and Distributed Systems, Vol 15, No 6, pp. 481-490, June 2004. 50% own contribution

V. A. Chouliaras, J.L. Nunez-Yanez, 'Scalar Coprocessors for accelerating the G723.1 and G729A Speech Coders', IEEE Transactions on Consumer Electronics, Vol 49, No. 3, pp. 703-710, August 2003. 50% own contribution

J.L Nunez-Yanez, S. Jones, ' Run-Length Coding Extensions for High Performance Hardware Data Compression',IEE Proceedings Computers&Digital Techniques, Vol. 150, No. 6, pp. 387-395, November 2003. 95% own contribution

J.L Nunez-Yanez, S. Jones, ' Gbit/Second Lossless Data Compression Hardware', IEEE Transactions in VLSI Systems (TVLSI), Vol. 11, No. 3, pp. 499-510, June, 2003, 95% own contribution

Conferences

Dave McEwan, Jose Nunez-Yanez, Relationship Estimation Metrics for Binary SoC Data, LOD2019, The Fifth International Conference on Machine Learning, Optimization, and Data Science – September 10-13, 2019, Italy

Dave McEwan, Marcin Hlond, Jose Nunez-Yanez, Visualizations for Understanding SoC Behaviour. PRIME 2019: 277-280, Lausanne, Switzerland, July 15-18

Mohammad Hosseinabady. Jose Nunez-Yanez, Heterogeneous FPGA+GPU Embedded Systems: Challenges and Opportunities, HIP3ES: High Performance Energy Efficient Embedded Systems Workshop 7th Edition, HiPEAC, Valencia, 2019

W. Beasley, B. Gatusch, D. Connolly-Taylor, C. Teng, A. Marzo and J. Nunez-Yanez, "Ultrasonic Levitation with Software-Defined FPGAs and Electronically Phased Arrays," 2019 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), Colchester, United Kingdom, 2019, pp. 41-48.

Jose Nunez-Yanez, Mohammad Hosseinabady, Moslem Amiri, Andrés Rodríguez, Rafael Asenjo, Angeles Navarro, Rubén Gran-Tejero, Darío Suárez-Gracia. “Parallelizing Workload Execution in Embedded and High-Performance Heterogeneous Systems”, HIP3ES: High Performance Energy Efficient Embedded Systems Workshop 6th Edition, HiPEAC, Manchester, 2018

Sam Amiri, Mohammad Hosseinabady, Andres Rodriguez, Rafael Asenjo, Angeles Navarro and Jose Nunez-Yanez, "Workload Partitioning Strategy for Improved Parallelism on FPGA-CPU Heterogeneous Chips", FPL18, Dublin, September 2018

Amiri, S, Hosseinabady, M, McIntosh-Smith, S & Nunez-Yanez, J, 2018, ‘Multi-precision convolutional neural networks on heterogeneous hardware’. in: Design, Automation & Test in Europe Conference & Exhibition (DATE), 2018. Institute of Electrical and Electronics Engineers (IEEE), pp. 419-424

Hosseinabady, M & Nunez-Yanez, JL, 2018, ‘Pipelined Streaming Computation of Histogram in FPGA OpenCL’. in: Parallel Computing is Everywhere. IOS Press BV, pp. 632-641

Nunez-Yanez, J, Hosseinabady, M, Rodríguez, A, Asenjo, R, Navarro, A, Gran-Tejero, R & Suárez-Gracia, D, 2018, ‘Simultaneous Multiprocessing on a FPGA+CPU Heterogeneous System-On-Chip’. in: Parallel Computing is Everywhere. IOS Press BV, pp. 677-686

M. Hosseinabady, Nunez-Yanez, J. “A Systematic Approach to Design and Optimise Streaming Applications on FPGA Using High-Level Synthesis”, to appear at FPL conference, Ghent, Belgium, September 2017.

Yhang Zhang, Nunez-Yanez J, “Optimal Compression of Vibration Data with Lifting Wavelet Transform and Context-based Arithmetic Coding” to appear at EUSIPCO conference, Khos, Greece, August 2017.

Nunez-Yanez, J, ‘Computing to the limit with heterogeneous CPU-FPGA devices in a video fusion application’. in: Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Springer Verlag, pp. 41-53, 2016 (BEST PAPER AWARD)

Mohd Zainol, Nunez-Yanez J, CPCIe: ‘A Compression-enabled PCIe Core for Energy and Performance Optimization’, In IEEE Nordic Circuits and Systems conference (NORCAS), November, 2016, Copenhagen, Denmark

Awais Sani, Nunez-Yanez J, ‘Energy Proportional Computing with OpenCL on a FPGA-Based Overlay Architecture’, In IEEE Nordic Circuits and Systems conference (NORCAS), November, 2016, Copenhagen, Denmark

Peng Sun, Alin Achim, Ian Hasler, Paul Hill and Jose Nunez-Yanez, 'Energy Efficient Video Fusion with Heterogenous CPU-FPGA device', published in Design Automation and Test in Europe, (DATE 2016), Dresden, Germany

M. Hosseinabady and J. L. Nunez-Yanez, "Energy optimization of FPGA-based stream-oriented computing with power gating," 2015 25th International Conference on Field Programmable Logic and Applications (FPL), London, 2015, pp. 1-6., doi: 10.1109/FPL.2015.7293946

M. Hosseinabady and J. L. Nunez-Yanez, "Optimised OpenCL workgroup synthesis for hybrid ARM-FPGA devices," 2015 25th International Conference on Field Programmable Logic and Applications (FPL), London, 2015, pp. 1-6., doi: 10.1109/FPL.2015.7294016

K. Nikov, J. L. Nunez-Yanez and M. Horsnell, "Evaluation of Hybrid Run-Time Power Models for the ARM Big.LITTLE Architecture," Embedded and Ubiquitous Computing (EUC), 2015 IEEE 13th International Conference on, Porto, 2015, pp. 205-210.doi: 10.1109/EUC.2015.32

Nunez-Yanez, J, Beldachi, Arash Farhadi "Run-time power and performance scaling with CPU-FPGA hybrids", NASA/ESA Adaptive Hardware and Systems conference, Leicester, UK, July 2014. (Obtained the conference Best Paper Award) (90% own contribution)

Nunez-Yanez, J., "Energy efficient Reconfigurable Computing with Adaptive Voltage and Logic scaling", HEART (Highly Efficient Accelerators and Reconfigurable Technology), Sendai, Japan, June, 2014, 100% own contribution

Peng Sun, Jose Nunez-Yanez, Optimizing Memory Power in Hybrid ARM-FPGA Chips With Lossless Data Compression, FPGAWorld, Sweeden, September, 2014, 50% own contribution

Mohammad Hosseinabady and Jose Luis Nunez-Yanez, Run-Time Power Gating in Hybrid ARM-FPGA Devices, Field Programmable Logic (FPL) 2014, Munich, September 2-4th, 2014, 50% own contribution

Arash beldachi and Jose Luis Nunez-Yanez, Accurate Power control and monitoring in ZYNQ boards, Field Programmable Logic (FPL) 2014, Munich, September 2-4th, 2014, 30% own contribution

Juan Carlos Moctezuma, Jose Luis Nunez-Yanez and Joseph P. McGeehan, Neuron Dynamics of Two-compartment Traub Model for Hardware-based Emulation, international conference on neural computation theory and applications 2014, Rome, 22-25 October, 2014, 50% own contribution

Jin chen, Jose Nunez-Yanez, Alin Achim, Joint Video Fusion and Super Resolution Based on Markov Random Fields, IEEE international conference on image processing, Paris, October 27-30, 2014, 100% own contribution

Wu, Y., Nunez-Yanez, J., Woods, R. & Nikolopoulos, D. Power Modeling and Capping for Heterogeneous ARM/FPGA SoCs 2014 Proceedings of the 2014 International Conference on Field- Programmable Technology (FPT). IEEE Computer Society, p. 1, , 20% own contribution

Jin Chen, Jose Nunez-Yanez , and Alin Achim, “Video super-resolution using low rank matrix completion”, IEEE international conference on image processing, ICIP’13, Melbourne, Australia. pp. 1376-1380. 30% own contribution

Moctezuma, J.C.; McGeehan, J.P.; Nunez-Yanez, J.L., "Numerically efficient and biophysically accurate neuroprocessing platform," Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference on , vol., no., pp.1,6, 9-11 Dec. 2013, doi: 10.1109/ReConFig.2013.6732313, 20% own contribution

Jose Nunez-Yanez. 2013. Energy proportional computing in commercial FPGAs with adaptive voltage scaling. In Proceedings of the 10th FPGAworld Conference (FPGAworld '13). ACM, New York, NY, USA, , Article 6 , 5 pages. DOI=10.1145/2513683.2513689 . 100% own contribution

Jin Chen, Jose Nunez-Yanez and Alin Achim, “Approximate Alpha-stable Markov Random Fields for Video Super-resolution”, 20th European Signal Processing Conference (EUSIPCO 2012), Bucharest, Romania, August 27-31, 2012. 30% own contribution

José L. Núñez-Yáñez, Arash Beldachi, Atukem Nabina, Mohammad Hosseinabady, “Exploring dynamically reconfigurable multicore designs with NoRC designer”. HPCS (High Performance Computing and Simulation) conference, 2012: pp. 254-260, June 3rd- 5th. Madrid, Spain, 2012. 70% own contribution

Arash Farhadi Beldachi and Jose L. Nunez-Yanez. 2012. Reconfigurable router design and evaluation for the FPGA-friendly SoCWire network-on-chip. In Proceedings of the Annual FPGA Conference (FPGAworld '12). ACM, New York, NY, USA, , Article 1 , 6 pages. DOI=10.1145/2451636.2451637. 30% own contribution

Mohammad Hosseinabady, and Jose Nunez-Yanez, “Effective Modelling of Large NoCs using SystemC” IEEE International Symposium on Circuits and Systems ISCAS’10, pp. 161-164, Paris, May 30- June 2, 2010. 30% own contribution

Mohammad Hosseinabady, Jose L. Nunez-Yanez, Antonio Marcello Coppola, "Task Dispersal Measurement in Dynamic Reconfigurable NoCs," isvlsi, pp.167-172, 2010 IEEE Annual Symposium on VLSI, 2010. 30% own contribution

Mohammad Hosseinabady, and Jose Nunez-Yanez, “SystemC Architectural Transaction Level Modelling for Large NoCs”, Forum on specification & Design Languages (FDL’10), pp. 142-147, Southampton, UK, Sept 14-16, 2010. 30% own contribution

T.Spiteri,G.Vafiadis, and Jose Nunez-Yanez, “Flexible motion estimation processors for high definition video coding," in Fifth UK Embedded Forum, Sep. 2009, pp. 24-29. 30% own contribution

Atukem Nabina, Jose Nunez-Yanez, "Dynamic Reconfiguration Optimisation with Streaming Data Decompression," fpl, pp.602-607, 2010 International Conference on Field Programmable Logic and Applications, 2010. 30% own contribution

Jose Nunez-Yanez, Trevor Spiteri and George Vafiadis, 'Fast Motion Estimation using Configurable and Extendable Processing Cores', IEEE 43rd Asilomar Conference on Signals, Systems and Computers, Monterey, CA, USA, November 1- November 4, 2009. 30% own contribution

Wei Song, Doug Edwards, Jose Nunez-Yanez, and Sohini Dasgupta. ‘Adaptive stochastic routing in fault-tolerant on-chip networks’. 3rd ACM/IEEE International Symposium on Networks-on-Chip NOCs, May 10-May 13 Pages 32-37, La Jolla, CA, USA, 2009. 20% own contribution.

Jose Nunez-Yanez, ‘Energy Optimization in a Network-On-Chip with Dynamically Reconfigurable Processing Nodes’, Invited paper, 2009 IEEE Multi-conference on Systems and Control, pp. 308-313, July 8-10, 2009, Saint Petersburg, Russia. 95% own contribution.

Yiwei Zhang, José Nuñez-Yañez, Joe McGeehan, Edward Regan and Stephen Kelly, ‘A Biophysically Accurate Floating Point Somatic Neuroprocessor’, 19th International conference on Field Programmable Logic and Applications, pp. 26-31, Czech Republic, Prague, August 29- September 2, 2009. 30% own contribution.

Mohammad Hosseinabady and Jose L. Nunez-Yanez, ‘Run-Time Resource Management in Fault-Tolerant Network on Reconfigurable Chips’, 19th International conference on Field Programmable Logic and Applications, pp. 574-577, Czech Republic, Prague, August 29- September 2, 2009. 20% own contribution

Trevor Spiteri, George Vafiadis and Jose Luis Nunez-Yanez, ‘A Toolset for the Analysis and Optimization of Motion Estimation Algorithms and Processors’, 19th International conference on Field Programmable Logic and Applications, pp. 423-427, Czech Republic, Prague, August 29- September 2, 2009. 30% own contribution.

Nunez-Yanez, J.L.; Hung, E.; Chouliaras, V., ‘A configurable and programmable motion estimation processor for the H.264 video codec,’ Field Programmable Logic and Applications, 2008. FPL 2008. International Conference on , vol., no., pp.149-154, 8-10 Sept. 2008. 95% own contribution.

(invited paper) Jose L. Nunez-Yanez, Xiaolin Chen, Nishan Canagarajah, Raffaele Vitulli, 'Statistical Lossless Compression of Space Imagery and General Data in a Reconfigurable Architecture', 2008 NASA/ESA conference on Adaptive Hardware Systems, pp. 172-178, 22-25 June, Noordwijjk, Netherlands, 2008. 95% own contribution.

Mohammad Hosseinabady and Jose Nunez-Yanez. 'Fault-tolerant dynamically reconfigurable NoC-based SoC.' ASAP'08 19th IEEE International Conference Application-specific Systems, Architectures and Processors, Leuven, Belgium, June, 2008. 30% own contribution.

Xiaolin Chen, Nishan Canagarajah, Raffaele Vitulli, Jose L. Nunez-Yanez, 'Lossless Compression for Space Imagery in a Dynamically Reconfigurable Architecture', Applied Reconfigurable Computing Workshop (ARC), LNCS 4943, March, London, pp. 336-341, 2008. 30% own contribution.

Zaidi, Izhar; Nabina, Atukem; Canagarajah, C.N.; Nunez-Yanez, Jose, ‘Power/Area Analysis of a FPGA-Based Open-Source Processor using Partial Dynamic Reconfiguration,’ Digital System Design Architectures, Methods and Tools, 2008. DSD '08. 11th EUROMICRO Conference on , vol., no., pp.592-598, 3-5 Sept. 2008. 30% own contribution.

Zaidi, I.; Nabina, A.; Canagarajah, C.N.; Nunez-Yanez, J., ‘Evaluating dynamic partial reconfiguration in the integer pipeline of a FPGA-based open-source processor,’ Field Programmable Logic and Applications, 2008. FPL 2008. International Conference on , vol., no., pp.547-550, 8-10 Sept. 2008. 30% own contribution

(Best Paper Award) X. Chen, N. Canagarajah and J. L. Nunez-Yanez. 'Lossless Multi-mode Interband Image Compression and its Hardware Architecture' Conference on Design and Architectures for Signal and Image Processing (DASIP 2008), Brussels, Belgium, November, 2008. 30% own contribution.

Nunez-Yanez, J. Eddie Hung, Xiaolin Chen, Nishan Canagarajah, 'A Configurable Pixel and Block Matching Motion Estimation Processor for Lossless and Lossy Video Compression,' On-board Payload Data Compression Workshop, 26-27 June, Noordwijk, The Netherlands, 2008. 95% own contribution.

Jose L. Nunez-Yanez, Vassilios A. Chouliaras, Jiri Gaisler, ‘Dynamic Voltage Scaling in a FPGA-based System-on-Chip’, International conference on Field Programmable Logic and Applications 2007, Amsterdam, Netherlands, pp. 459-462, 27-29 August, 2007.95% own contribution.

(invited paper) Jose L. Nunez-Yanez, Xiaolin Chen, Nishan Canagarajah, Raffaele Vitulli, ‘Dynamic Reconfigurable Hardware for Lossless Compression of Image, Video and General Data Content’, XXII Conference on Design of Circuits and Integrated Systems, pp. 564-569, November, Sevilla, Spain, 2007, ISBN-13 978-84690-8629-2. 95% own contribution.

Xiaolin Chen, Nishan Canagarajah, Jose L. Nunez-Yanez, ‘Hardware Architecture for Lossless Image Compression Based on Context-based Modeling and Arithmetic Coding’, IEEE International SOC conference, September, Hsinchu Taiwan, pp. 251-254, 2007. 40% own contribution.

Robert Stapenhurst, Koushik Maharatna, Jimson Mathew, Jose Nunez-Yanez, “On the Hardware Reduction of Z-Datapath of Vectoring CORDIC” IEEE International Symposium of Circuits and Systems, 2007. 10% own contribution.

Koutsomyti, K., Chouliaras, V., Parr, S.R., Nunez-Yanez, J.L. and Datta, S., ''Accelerating Speech Coding Standards Through SystemC Synthesized SIMD and Scalar Accelerators'', IEEE 2006 International Conference on Consumer Electronics (ICCE 2006), IEEE, Las Vegas USA, pp. 279-280, 10th January 2006, . 10% own contribution.

Vassilios Chouliaras, J.L Nunez-Yanez, Tom Jacobs, Ashwin K. Kumaraswamy, ‘Configurable Multiprocessors for high-performance MPEG-4 video coding’, to appear in IEEE Computer Society Annual Symposium on VLSI 2005, May 11-12, 2005, Tampa, Florida, USA. 20% own contribution.

Ashwin K. Kumaraswamy,V. A. Chouliaras, T. R. Jacobs, and J. L. Nunez-Yanez, “System-on-Chip Design Framework (SDF) unifying Specification Capture and Design Modelling”, accepted for publication at the 2005 Electronic Design Processes (EDP) Workshop. 10% own contribution.

S. R. Parr, K. Koutsomyti, V. A. Chouliaras, J.L Nunez-Yanez, D. J. Mulvaney, ‘Configurable Scalar and Vector Coprocessors for Accelerating the G.723.1 and G.729A Speech Coders’ IASTED International Conference on SIGNAL AND IMAGE PROCESSING. ACIT-SIP 2005. 20% own contribution.

Tom R. Jacobs, Vassilios A. Chouliaras, J.L Nunez-Yanez ‘A Thread and Data-Parallel MPEG4 Video Encoder for a System-On-Chip Multiprocessor’, 16th IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05), pp. 405-410, 2005. 10% own contribution.

Jose L. Nunez-Yanez, Vassilios A. Chouliaras, ‘Design and Implementation of a High-Performance and Silicon Efficient Arithmetic Coding Accelerator for the H.264 Advanced Video Codec’, 16th IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05), pp. 411-416, 2005. 95% own contribution.

Chouliaras, V.A.; Flint, J.A.; Yibin Li; Nunez-Yanez, J.L., "A system-on-chip vector multiprocessor for transmission line modelling acceleration," Signal Processing Systems Design and Implementation, 2005. IEEE Workshop on , vol., no.pp. 568- 572, 2-4 Nov. 2005. . 10% own contribution.

V.A.Chouliaras, J.L Nunez-Yanez, S. Agha, ‘Silicon Implementation of Parametric Vector Datapath for Real-Time MPEG2 Encoding’, The sixth IASTED International Conference on Signal & Image Processing, pp. 298-304, Honolulu, Hawaii, 2004. 20% own contribution.

J.L Nunez-Yanez, V. A. Chouliaras, ‘Arithmetic Coding Hardware Acceleration in a SOPC Platform for Advanced Video Compression’, International Conference on Reconfigurable Computing and FPGAs, ReConFig04, Colima, Mexico, 2004. Best paper award ReconFIG 2004. 95% own contribution.

N.G. Bartzoudis, A.G. Fragkiadakis, D.J. Parish, J.L. Nunez-Yanez, ‘A System for Fault Detection and Reconfiguration of Hardware Based Active Networks’, 10th IEEE International On-Line Testing Symposium, Tivoli Ocean Park Hotel, Funchal, Madeira Island, Portugal, 2004. 20% own contribution.

T. R. Jacobs, V. A. Chouliaras, D. J. Mulvaney, J.L Nunez-Yanez, ‘The Application of Thread-Level Parallelism for Reducing the Architectural Complexity of an MPEG2 Encoder’, IEE/ACM SoC Design, Test and Technology Postgraduate Seminar, Loughborough University, Sept 2004 . 20% own contribution.

K. Koutsomyti, S. R. Parr, V. A. Chouliaras, J.L Nunez-Yanez, D. J. Mulvaney, S. Datta, ‘Scalar and Parametric Vector Accelerators for the G.729A Speech Coding Standard’, IEE/ACM SoC Design, Test and Technology Postgraduate Seminar, Loughborough University, Sept 2004. 20% own contribution.

E. G. Nikolova, D. J. Mulvaney, V. A. Chouliaras, J.L Nunez-Yanez, ‘A novel code compression decompression approach to high performance SoC design’, International Symposium on System-On-Chip design, Tampere, Finland, Nov 19-21, 2003. 20% own contribution M. Milward, J.L Nunez-Yanez, D. Mulvaney, ‘Routing Strategies for High-Speed Parallel Data Compression’, PDPTA 2003: Las Vegas, Nevada, USA – Volume 2, pp. 635-641, 2003. 30% own contribution.

N.G. Bartzoudis, A.G. Fragkiadakis, D.J. Parish, J.L Nunez-Yanez and M.J. Sandford, 'Reconfigurable Computing and Active Networks;, in Proceedings of The 2003 International Multiconference in Computer Science & Engineering (ERSA'03), Las Vegas, U.S.A., June 2003, pp. 280-284. 20% own contribution.

N.G. Bartzoudis, A.G. Fragkiadakis, D.J. Parish, J.L Nunez-Yanez, 'A Monitor Module for Active Networks with Hardware Support', IEE Seminar on SoC Design, Test and Technology, Cardiff University, Cardiff, UK, 2 September 2003. 20% own contribution.

E. G. Nikolova, D. J. Mulvaney, V. A. Chouliaras, J.L Nunez-Yanez, 'A Novel Code Compression/Decompression Approach for High-performance SoC Design', IEE Seminar on SoC Design, Test and Technology, Cardiff University, Cardiff, UK, 2 September 2003. 20% own contribution.

J.L Nunez-Yanez and S. Jones, 'Lossless Data Compression Programmable Hardware for High-Speed Data Networks', Proceedings of IEEE International Conference on Field-Programmable Technology (FPT), Hong Kong, China, pp. 290-293, December, 2002. 95% own contribution

R. Stefo, J.L Nunez-Yanez, C. Feregrino, S. Mahapatra, S. Jones, 'FPGA-based modelling unit for high speed lossless arithmetic coding', 11th International Conference on Field Programmable Logic and Applications FPL'2001, , Belfast, Northern Ireland, UK, August 27-29, 2001. 50% own contribution

J.L Nunez-Yanez, C. Feregrino, S. Bateman, S. Jones, 'The X-MatchLITE FPGA-Based Data Compressor', Proceedings of the 25th EUROMICRO Conference, Digital Systems Design: Architectures, Methods and Tools, pp. 126-132, September, 1999. 95% own contribution

J.L Nunez-Yanez, S. Jones,'The X-MatchPRO 100 Mbytes/second FPGA-Based Lossless Data Compressor', Proceedings of Design, Automation and Test in Europe, DATE Conference 2000, pp.139-142, March, 2000. 95% own contribution

J.L Nunez-Yanez, S. Jones, S. Bateman, 'X-MatchPRO: A high performance full-duplex lossless data compressor on a ProASIC FPGA', Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications IDAACS'2001, 2001. 95% own contribution

J.L Nunez-Yanez, C. Feregrino, S. Jones, S. Bateman, 'X-MatchPRO: A ProASIC-Based 200 Mbytes/s Full-Duplex Lossless Data Compressor', pp. 613, 11th International Conference, FPL 2001, Belfast, Northern Ireland, UK, August 27-29, 2001. 95% own contribution

J.M. Moreno, J.L. Nunez-Yanez, J. Madrenas, J. Cabestany, J.R. Laúna. VLSI Implementation of a Neural Decision Engine for Commercial Coin Recognizers. Electron technology , 32 (3) : 266-271. 1999. 95% own contribution