Main unit contributions:

2nd year digital systems, 120 students, unit lead with 100% of load for both the taught (24 1-hour lectures) and laboratory part (8 sessions of 3-hour each) including developing the course to align with industry requirements, lectures (~85%) and labs (~15%),

2nd year EDA/CAD design unit (80 students), from 2004 to 2011, unit lead and unit developer. This unit is lab based and it was redesign in 2004 to align it with current industrial practice. The unit was designed to develop team skills and applying them to a challenging engineering problem in the area of digital design that must work in real hardware.

3rd year Embedded and real-time systems, 130 students, unit lead and unit developer with a 50% of total load (5 1-hour lectures and 8 sessions of 2-hour labs) , the unit is based on problem-based learning with a taught part consisting of lectures to support the learning process,

4th year/ MSc Advanced FPGA&DSP implementation. 50 students, unit lead and unit developer with 50% of total load (6 1-hour lectures and 6 2-hour labs). This unit focuses on state-of-the-art FPGA (Field Programmable Gate Arrays) micro-architecture and FPGA implementation tools. This unit takes place in a lab environment to create the immersion needed to follow the labs, designing, testing and verifying results in a supported close loop environment.

TSEA44 Computer Hardware - a System on Chip. 10 students, The course intends to give hands-on experience on the design of an advanced application specific computer system on a chip with regards to performance, response time, testability, cost and hardware/software interaction.

TSIU03- System Design,30 students. The course includes methods and tools for the design and implementation of electronic systems using VLSI technologies. The design methods aim at reducing the design time and guarantee correct designs as well as ensuring that performance requirements are met. The course teaches behavioral description using VHDL combined with automatic synthesis of logic and implementation targeting FPGA technologies.

TSEA85, Hardware Design for Machine Learning Acceleration. 20 students. This master course intends to give hands-on experience on the design of an advanced machine learning accelerator using reconfigurable hardware with a focus on performance, debugging, memory and interaction between hardware and software.

Advanced FPGA implementation, 5 students. This PhD course explores initially the architecture and features of modern FPGAs. Then, it teaches how to use C-based high level synthesis as an alternative to traditional Verilog/VHDL RTL design. The VITIS HLS and VIVADO synthesis and implementation tools will target a SoC Zynq FPGA that includes, in addition to the configurable logic, an ARM-based processing system. A final project completes the learning objectives by designing a hardware accelerator suitable for large general matrix multiplications in a resource-constrained PYNQ-Z2 board.